Developing a superconducting computer that would perform computations at high speed without heat dissipation has been the goal of several research and development initiatives since the 1950s. Such a computer would require a fraction of the energy current supercomputers consume, and would be many times faster and more powerful. Despite promising advances in this direction over the last 65 years, substantial obstacles remain, including in developing miniaturized low-dissipation memory.
Researchers at the University of Illinois at Urbana-Champaign have developed a new nanoscale memory cell that holds tremendous promise for successful integration with superconducting processors. The new technology, created by Professor of Physics Alexey Bezryadin and graduate student Andrew Murphy, in collaboration with Dmitri Averin, a professor of theoretical physics at State University of New York at Stony Brook, provides stable memory at a smaller size than other proposed memory devices.
Written by Siv Schwink
Professor Alexey Bezryadin works in the lab with graduate student Andrew Murphy, at the Loomis Laboratory of Physics in Urbana. Photo by Siv Schwink, Physics IllinoisDeveloping a superconducting computer that would perform computations at high speed without heat dissipation has been the goal of several research and development initiatives since the 1950s. Such a computer would require a fraction of the energy current supercomputers consume, and would be many times faster and more powerful. Despite promising advances in this direction over the last 65 years, substantial obstacles remain, including in developing miniaturized low-dissipation memory.
Researchers at the University of Illinois at Urbana-Champaign have developed a new nanoscale memory cell that holds tremendous promise for successful integration with superconducting processors. The new technology, created by Professor of Physics Alexey Bezryadin and graduate student Andrew Murphy, in collaboration with Dmitri Averin, a professor of theoretical physics at State University of New York at Stony Brook, provides stable memory at a smaller size than other proposed memory devices.
The device comprises two superconducting nanowires, attached to two unevenly spaced electrodes that were “written” using electron-beam lithography. The nanowires and electrodes form an asymmetric, closed superconducting loop, called a nanowire ‘SQUID’ (superconducting quantum interference device). The direction of current flowing through the loop, either clockwise or counterclockwise, equates to the “0” or “1” of binary code.
The memory state is written by applying an oscillating current of a particular magnitude, at a specific magnetic field. To read the memory state the scientists ramp up the current and detect the current value at which superconductivity gets destroyed. It turns out that such destruction or critical current is different for the two memory states, “0” or “1”. The scientists tested memory stability, delaying reading of the state, and found no instances of memory loss. The team performed these experiments on two nanowire SQUIDS, made of the superconductor Mo75Ge25, using a method called molecular templating. The results are published in the June 13, 2017 New Journal of Physics (v.19, p.063015).
Superconducting nanoscale memory cell. Binary information is encoded in the direction of the electrical current in the loop. Clockwise indicates '0', counter clockwise, '1'. The superconducting electrons flow indefinitely, so memory is nonvolatile. (a) Photo of device: A superconducting strip of Mo75Ge25 (yellow) with a pair of superconducting nanowires forming a closed loop (also yellow). (b) The critical current (maximum current that can be injected without destroying superconductivity) plotted as a function of magnetic field: To set the memory state '0', a positive current is applied, targeting the shaded diamond. To set the memory to '1', a negative current is applied. To read out the state, the current is ramped, as shown by the red rhombus, and the current value at which voltage occurs is measured. This measured value, the critical current, depends on the pre-set memory; its statistical distribution is shown in (c). Images by Bezryadin and Murphey, U. of I. at Urbana-ChampaignBezryadin comments, “This is very exciting. Such superconducting memory cells can be scaled down in size to the range of few tens of nanometers, and are not subject to the same performance issues as other proposed solutions.”
Murphy adds, “Other efforts to create a scaled-down superconducting memory cell weren’t able to reach the scale we have. A superconducting memory device needs to be cheaper to manufacture than standard memory now, and it needs to be dense, small, and fast.”
Up to now, the most promising supercomputing memory devices, called ‘single-flux quanta’ devices, rely on manipulating circuits composed of Josephson junctions and inductive elements. These are in the micrometer range, and miniaturization of these devices is limited by the size of the Josephson junctions and their geometric inductances. Some of these also require ferromagnetic barriers to encode information, where Bezryadin and Murphy’s device does not require any ferromagnetic components and eliminates magnetic-field cross-talk.
“Because the kinetic inductance increases with decreasing cross-sectional dimensions of the wire, nanowire SQUID memory elements could be reduced further, into the range of tens of nanometers,” Bezryadin continues.
The researchers argue that this device can operate with a very low dissipation of energy, if the energies of two binary states are equal or near equal. The theoretical model for such operations was developed in collaboration with Averin. The switching between the states of equal energy will be achieved either by quantum tunneling or by adiabatic processes composed of multiple jumps between the states.
In future work, Bezryadin plans to address the measurements of the switching time and to study larger arrays of the nanowire squids functioning as arrays of memory elements. They will also test superconductors with higher critical temperatures, with the goal of a memory circuit that would operate at 4 Kelvin. Rapid operations will be achieved by utilizing microwave pulses.
This research is supported by the National Science Foundation, Division of Electrical, Communications and Cyber Systems.